A Versatile Netlist Generator for Fast Datapath Processing Slices Basing on Tree Representations

G. Heinz

Lecture series at Sican GmbH* Hannover
starting on June 5, 1991

To accelerate the pipelining of parallel, digital circuits in arithmetic units of processors, the delays on different bit-paths have to be balanced out. Between 1988 and 1990 at the "Akademie der Wissenschaften der DDR, Zentralinstitut für Kybernetik und Informationsprozesse (AdW-ZKI)" we developed solutions basing on fastest tree-structures. Tree-like representations allow a balanced delay mapping in standard cell layout or logic structures of FPGAs. The general idea was, to harmonize the delay on each bit-path to get very higher speed for pipelining.

The slides represent the results of the last research project (1990) of my research group with Friedrich-Karl Staats, Dr. Helmut Jahne, Dr. Juergen Sieck, Torsten Hoffmeister and Uwe Schroeder.

Especially the acceleration of pipelining for design-automated standard-cell architectures seems us valueable for new, faster generations of microprocessors.

Different copies of the C-sources and the slides went to design centers of eminent companies, like VLSI-Technology, Intel, Mentor and Cadence. However, the idea maight not only have accelerated the speed of microcontrollers, it also could have inspired the development of VHDL-synthesizer tools.

In the years of re-unification we had no spirit to write a paper about this theme. Only the overhead slides left after 15 years. Direct after re-unification the AdW-ZKI was closed. In April 1991 I went to Hannover to work with for the new SICAN design center (2006: Infineon/Sci-Works). The first ASIC for Sican* (1991) was a 330.000 transistor HDTV-image processor for Digital Video Systems Hannover, inspired by tree generation ideas.

Presentation (46 overhead-slides)

page 01-06, 1.5 MB, Introduction

page 07-14, 1.2 MB, About Tree Structures

page 15-28, 3.9 MB, Design Example

page 29-38, 1.9 MB, How a Generator Works

page 39-46, 1.3 MB, Possible applications

Further infos see a introduction (PDF) and test examples (PDF).

*Sican GmbH, Garbsener Landstr. 10, W-3000 Hannover 21, was foundet under Gerhard Schröder 1989/1990 as an integrated circuit design centre for the "Land Niedersachsen". The first integrated circuit design of Sican in 1991 was "SPOC", a video frame manipulation circuit for Digital Video Systems GmbH (DVS) Hannover with 330.000 transistors. We used Cadence design tools, Edge2.1 and Solo2030 CMOS-cell library and production service of ES2 (European Silicon Structures Mount Lane, Bracknell, Berkshire, UK). Project manager was Dr. Gerd Heinz, first developers were designers from Funkwerk Erfurt (MME/FWE).


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